Stacked Die

The major market drivers for stacked die applications are reduced space, weight savings and enhanced electrical performance of the devices (which are mainly used in portable consumer products). Stacking of chips, in which two or more ICs of different types are placed at the same coordinates in the x-y plane, is an alternative to silicon integration. The memory industry has discovered this opportunity to minimize package size and cost by stacking one die on top of the other in a single package. Such a system usually consumes less power and features higher speed than separate components. Stacked die applications provide flexibility in combining different devices without touching the design level of the silicon. Time to market can be drastically reduced. Additionally, the functionality of the device can be doubled or tripled in the same package size.

The vertically integrated system in a package has a much higher package integration ratio compared to the single die solution. In addition, the electrical performance and reliability of stacked die is improved because only one package has to be tested, and established IC assembly methods can be used.

Challenges of Stacked Die

To stay within standard package heights, the stacked chips need to be thinned. The backgrinding process is used to reduce the die thickness to the range of 50 - 125 µm. As a result, wafer handling needs special attention. Thus, a gentle and controlled die pick-up procedure is needed. Thin large die have a tendency to warp, which causes problems during the die bond process. Special tooling and techniques are required to keep the die flat on the substrate.

For the stacked die process, high die placement accuracy is essential to mount the upper chip accurately onto the lower one. Inaccurate die placement can lead to electrical failure (wire shorts) and impacts the epoxy bleed out. Since another cause of epoxy bleed-out is poor dispense quality, the position and volume of the dispensed epoxy needs to be consistent. Excessive epoxy may cover the wire bonding pads, preventing a proper interconnection. Using backside-coated wafers eliminates this problem since the adhesive is evenly spread on the backside of the top die and no epoxy/die offset can occur. This benefit makes the backside wafer process very attractive for stacked die. It is important to consider, however, that this process needs immediate curing, which may reduce productivity. Depending on the process applied (paste form adhesive), a curing step is required before the second die can be attached. However, curing often warps the substrate. Special downhold methods are required to keep the substrate in place for an accurate second die placement. For wire bonding applications, the substrate design rules and the loop height have to be carefully monitored to prevent a wire from shorting between the two die.

The back-end process: Step 4 - Die attach
Today's challenges

BY PETER BÜHLMANN AND DOMENICO TRUNCELLITO

The Most Common Processes

There are four major die attach processes used in semiconductor packaging.

Eutectic Die Attach: The eutectic die attach process is a well-established bonding technique, having been used in the early days of semiconductors for the first transistors and integrated cicuits (IC). It is still widely used for small signal products - so called "jelly beans" - manufactured by the millions every day. Currently, eutectic die attach has regained importance in the field of packaging optoelectronic components and high-power communication devices. Under high temperature, the silicon-gold combination forms the eutectic bond. A scrub motion during the bond process increases the strength and quality of the intermetallic connection between the chip and substrate. For large chips, additional gold in ribbon form is used. Because of the high temperature of the process (up to 450°C), a protective forming gas atmosphere (a nitrogen/ hydrogen combination) is needed to prevent oxidation of the lead frame.

Soft Solder Die Attach: This process uses a solder material to bond the die to the lead frame. The solder is introduced as a wire preform and melted onto the hot lead frame surface as a liquid solder dot. A chip is placed on the hot solder and as soon as the solder cools down, a solid connection is established. These solders are typically lead- and tin-based alloys. A controlled temperature profile is required to define the liquidus/ solidus transition. Again, a protective forming gas atmosphere is required to prevent oxidation of the lead frame. Soft solder applications are typically used in automotive and high-power devices.

Flip Chip Bonding: A process similar to soft solder die attach is used in flip chip bonding. Here, the chip is flipped before being attached, and solder bumps between the chip and substrate serve as both an electrical and mechanical interconnection. Drivers for this process are high I/O counts and increased electrical performance requirements for high-speed, high-frequency applications.

Tape and Other Die Attach Processes: For some special applications, such as large memory devices, different tapes are used as the adhesive (epoxy, polyimides and thermoset/thermoplastic materials). The latest trend is to apply the adhesive directly to the backside of a wafer instead of using tape as an adhesive carrier. Wafer backside coating provides clear advantages for thin die and stacked die applications, because the adhesive is spread evenly on the bottom of the chip and it is always in the right position.

Epoxy Die Attach: Epoxy die attach is the most commonly used process, and the term generally encompasses the use of other adhesives, such as polyimide- or silicone-based materials. The adhesive is dispensed in paste form on the bond pad of the lead frame or substrate before die placement. Typical applications using epoxy cover a wide range of devices, from simple transistors to high power processors, memory and ASICs.

Today's packaging technologies create challenges for epoxy die attach processes. The key criteria for success (such as productivity and material cost) are not as crucial in advanced packaging. The challenges in this segment lie within the process and its execution.