Stacked Die

The major market drivers for stacked die applications are reduced space, weight savings and enhanced electrical performance of the devices (which are mainly used in portable consumer products). Stacking of chips, in which two or more ICs of different types are placed at the same coordinates in the x-y plane, is an alternative to silicon integration. The memory industry has discovered this opportunity to minimize package size and cost by stacking one die on top of the other in a single package. Such a system usually consumes less power and features higher speed than separate components. Stacked die applications provide flexibility in combining different devices without touching the design level of the silicon. Time to market can be drastically reduced. Additionally, the functionality of the device can be doubled or tripled in the same package size.

The vertically integrated system in a package has a much higher package integration ratio compared to the single die solution. In addition, the electrical performance and reliability of stacked die is improved because only one package has to be tested, and established IC assembly methods can be used.

Challenges of Stacked Die

To stay within standard package heights, the stacked chips need to be thinned. The backgrinding process is used to reduce the die thickness to the range of 50 - 125 µm. As a result, wafer handling needs special attention. Thus, a gentle and controlled die pick-up procedure is needed. Thin large die have a tendency to warp, which causes problems during the die bond process. Special tooling and techniques are required to keep the die flat on the substrate.

For the stacked die process, high die placement accuracy is essential to mount the upper chip accurately onto the lower one. Inaccurate die placement can lead to electrical failure (wire shorts) and impacts the epoxy bleed out. Since another cause of epoxy bleed-out is poor dispense quality, the position and volume of the dispensed epoxy needs to be consistent. Excessive epoxy may cover the wire bonding pads, preventing a proper interconnection. Using backside-coated wafers eliminates this problem since the adhesive is evenly spread on the backside of the top die and no epoxy/die offset can occur. This benefit makes the backside wafer process very attractive for stacked die. It is important to consider, however, that this process needs immediate curing, which may reduce productivity. Depending on the process applied (paste form adhesive), a curing step is required before the second die can be attached. However, curing often warps the substrate. Special downhold methods are required to keep the substrate in place for an accurate second die placement. For wire bonding applications, the substrate design rules and the loop height have to be carefully monitored to prevent a wire from shorting between the two die.